1. Field of the Invention
This invention relates to electronic testing devices and, more particularly, to a method and apparatus for calibrating linear delay lines in a VLSI tester.
2. Description of the Related Art
When testing integrated circuits, the time marker signals which are used to form the test signals must be accurately placed within prescribed time intervals. The time intervals typically comprise the periods of a system clock signal. It is not uncommon to find system clock periods on the order of 3.2 nanoseconds, and this frequently results in a required marker placement resolution on the order of picoseconds.
Because of the magnitude of the required resolution, it is usually necessary to employ linear delay lines rather than gated digital circuits for marker placement. Such a delay line is illustrated in FIG. 1. As shown in FIG. 1, a delay circuit 10 comprises a range digital-to-analog converter (DAC) 14 for converting a digital word into a charging current on a line 18; an integrator 22 for converting the current on line 18 into a ramp voltage on line 2610; a delay DAC 30 for converting a digital word into a reference voltage on a line 34; and a comparator 38 for comparing the range voltage on line 26 with the reference voltage on line 34 and for producing a signal on a line 42 when the range voltage matches the reference voltage. Once the range voltage matches the reference voltage, integrator 22 may be reset by signals applied to a reset line 46.
Operation of delay circuit 10 may be understood by referring to FIG. 2. Delay DAC 30 produces a voltage V.sub.n on line 34, and range DAC 14 produces a current I.sub.c on line 18. At the beginning of each system clock period integrator 22 produces an increasing voltage from current I.sub.c on line 26. At time T.sub.n the voltage on line 26 matches the reference voltage V.sub.n on line 34, and a signal is provided on line 42 for indicating that fact. The time T.sub.n that it takes for the voltage produced by integrator 22 to reach V.sub.n determines the delay from the start of the clock pulse and hence determines the point within the clock period where the timing marker is to be placed.
Because of production tolerances and variations in the operating environment, the charging current I.sub.c, the reference voltage V.sub.n or the charging characteristics of integrator 22 may not be precise. For example, if the charging time of integrator 22 is smaller than expected, then, when a current I.sub.c (FIG. 2) is provided on line 18, a longer time T.sub.n, elapses before the reference voltage V.sub.n is matched. On the other hand, if the charging rate of integrator 22 is faster than expected, then a charging current I.sub.c " causes the voltage on line 26 to increase much faster, and hence a shorter time T.sub.n" elapses before the reference voltage V.sub.n is matched. Consequently, the actual range of delay times T.sub.n' or T.sub.n" may vary significantly from the theoretical range of delay time T.sub.n, and the circuit will not perform properly.